4T DRAM based on Self-controllable Voltage Level technique for low leakage power in VLSI

In present trend of integration will continue in the projected future. When comparing the integration density of integrated circuits, a clear distinction must be made between the memory chips and logic chips. Memory circuits are highly regular. Increase of chip complexity is consistently higher for memory circuits. The salient features such as low power, reliable performance, circuit techniques for high speed such as using dynamic circuits, and low leakage current, most of these have get give a better advantage. This paper gives an idea about 4T DRAM (dynamic random access memory) which is implemented by using a self controllable voltage level technique. In this technique reduces the leakage current and produce the high performance. Simulation is done by using a microwind 3.1 and DSCH3. Using a 90 nm technology to implemented a 4T DRAM. By using this give the benefit of 67% reduction of leakage current. This reduction gives a advantage of high performance and low leakage current, by controlling these parameter speed is automatically increase.